This invention relates to high-speed, register dominated integrated circuit designs. More particularly, this invention relates to an area optimized flip-flop for reducing the total area of the integrated circuit design.
In high-speed, register dominated integrated circuit designs, flip-flops make up a significant portion of the total design area. Thus, optimizing or reducing the area of flip-flops in these designs, may significantly improve the designs by reducing their total area and power consumption.
Other reduced area flip-flops have been proposed, but many of these reduced area flip-flops limit the testability of integrated circuit designs. For example, scan chain testing is one commonly used test technique. A group of flip-flops within an integrated circuit design may be interconnected to form a scan chain. Multiplexers may be used at the input of these flip-flops to alternatively receive ordinary inputs or scan chain inputs. When a scan chain is formed with a group of flip-flops, a test pattern or vector may be shifted into the scan chain. After the test vector is shifted into the scan chain, the test vector may be allowed to propagate through select sequential and combinatorial elements of the design. The result may be shifted out of the chip through the same or a different scan chain and may be analyzed to detect errors in a chip fabricated from the design. The scan chain test is only one example of a design-for-test (DFT) technique, whereby an integrated circuit may be designed specifically to facilitate future testing of the finished chip.
In view of the forgoing, it would be desirable to be able to provide an area optimized edge-triggered flip-flop for high speed memory dominated designs that can reduce the total area of the design without significantly limiting the testability of the design. In particular, it would be desirable to provide an area optimized edge-triggered flip-flop for high speed memory dominated design that may be used in conjunction with a scan chain test.